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? 2008-2013 microchip technology inc. ds20002123d-page 1 25aa02e48/25AA02E64 device selection table features: ? pre-programmed globally unique, 48-bit or 64-bit node address ? compatible with eui-48? and eui-64? ? 10 mhz max. clock frequency ? low-power cmos technology: - max. write current: 5 ma at 5.5v - read current: 5 ma at 5.5v, 10 mhz - standby current: 1 ? a at 2.5v ? 256 x 8-bit organization ? write page mode (up to 16 bytes) ? sequential read ? self-timed erase and write cycles (5 ms max.) ? block write protection: - protect none, 1/4, 1/2 or all of array ? built-in write protection: - power-on/off data protection circuitry - write enable latch - write-protect pin ? high reliability: - endurance: 1,000,000 erase/write cycles - data retention: >200 years - esd protection: >4000v ? temperature ranges supported: ? pb-free and rohs compliant package types (not to scale) description: the microchip technology inc. 25aa02e48/ 25AA02E64 (25aa02exx*) is a 2 kbit serial electri- cally erasable programmable read-only memory (eeprom). the memory is accessed via a simple serial peripheral interface (spi) compatible serial bus. the bus signals required are a clock input (sck) plus separate data in (si) and data out (so) lines. access to the device is controlled through a chip select (cs ) input. communication to the device can be paused via the hold pin (hold ). while the device is paused, transi- tions on its inputs will be ignored, with the exception of chip select, allowing the host to service higher priority interrupts. the 25aa02exx is available in the standard 8-lead soic and 6-lead sot-23 packages. pin function table part number v cc range page size temp. ranges packages node address 25aa02e48 1.8-5.5v 16 bytes i sn, ot eui-48? 25AA02E64 1.8-5.5v 16 bytes i sn, ot eui-64? - industrial (i): -40 ? cto +85 ? c cs so wp v ss 1 2 3 4 8 7 6 5 v cc hold sck si (sn) soic v ss 1 2 3 4 6 5 v dd cs so (ot) sot-23 sck si name function cs chip select input so serial data output wp write-protect v ss ground si serial data input sck serial clock input hold hold input v cc supply voltage 2k spi bus serial eeproms with eui-48? or eui-64? node identity *25aa02exx is used in this document as a generic part number for the 25aa02e48/25AA02E64 devices.
25aa02e48/25AA02E64 ds20002123d-page 2 ? 2008-2013 microchip technology inc. 1.0 electrical characteristics absolute maximum ratings (?) v cc ............................................................................................................................... ..............................................6.5v all inputs and outputs w.r.t. v ss ......................................................................................................... -0.6v to v cc +1.0v storage temperature ............................................................................................................ .....................-65c to 150c ambient temperature under bias ................................................................................................. ................-40c to 85c esd protection on all pins ..................................................................................................... .....................................4 kv table 1-1: dc characteristics ? notice : stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for an extended period of time may affect device reliability. dc characteristics industrial (i): t a = -40c to +85c v cc = 1.8v to 5.5v param. no. sym. characteristic min. max. units test conditions d001 v ih 1 high-level input voltage 0.7 v cc v cc +1 v d002 v il 1 low-level input voltage -0.3 0.3 v cc vv cc ??? 2.7v ( note 1 ) d003 v il 2 -0.3 0.2 v cc vv cc < 2.7v ( note 1 ) d004 v ol low-level output voltage ?0.4vi ol = 2.1 ma d005 v ol ?0.2vi ol = 1.0 ma, v cc < 2.5v d006 v oh high-level output voltage v cc -0.5 ? v i oh = -400 ? a d007 i li input leakage current ?1 ? acs = v cc , v in = v ss or v cc d008 i lo output leakage current ?1 ? acs = v cc , v out = v ss or v cc d009 c int internal capacitance (all inputs and outputs) ?7pft a = 25c, clk = 1.0 mhz, v cc = 5.0v ( note 1 ) d010 i cc read operating current ? ? 5 2.5 ma ma v cc = 5.5v; f clk = 10.0 mhz; so = open v cc = 2.5v; f clk = 5.0 mhz; so = open d011 i cc write ? ? 5 3 ma ma v cc = 5.5v v cc = 2.5v d012 i ccs standby current ? 1 ? acs = v cc = 2.5v, inputs tied to v cc or v ss , t a = +85c note: this parameter is periodically sampled and not 100% tested.
? 2008-2013 microchip technology inc. ds20002123d-page 3 25aa02e48/25AA02E64 table 1-2: ac characteristics ac characteristics industrial (i): t a = -40c to +85c v cc = 1.8v to 5.5v param. no. sym. characteristic min. max. units test conditions 1f clk clock frequency ? ? ? 10 5 3 mhz mhz mhz 4.5v ?? v cc ? 5.5v 2.5v ?? v cc ? 4.5v 1.8v ?? v cc ? 2.5v 2t css cs setup time 50 100 150 ? ? ? ns ns ns 4.5v ?? v cc ? 5.5v 2.5v ?? v cc ? 4.5v 1.8v ?? v cc ? 2.5v 3t csh cs hold time 100 200 250 ? ? ? ns ns ns 4.5v ?? v cc ? 5.5v 2.5v ?? v cc ? 4.5v 1.8v ?? v cc ? 2.5v 4t csd cs disable time 50 ? ns ? 5 tsu data setup time 10 20 30 ? ? ? ns ns ns 4.5v ?? v cc ? 5.5v 2.5v ?? v cc ? 4.5v 1.8v ?? v cc ? 2.5v 6t hd data hold time 20 40 50 ? ? ? ns ns ns 4.5v ?? v cc ? 5.5v 2.5v ?? v cc ? 4.5v 1.8v ?? v cc ? 2.5v 7t r clk rise time ? 100 ns ( note 1 ) 8t f clk fall time ? 100 ns ( note 1 ) 9t hi clock high time 50 100 150 ? ? ? ns ns ns 4.5v ?? v cc ? 5.5v 2.5v ?? v cc ? 4.5v 1.8v ?? v cc ? 2.5v 10 t lo clock low time 50 100 150 ? ? ? ns ns ns 4.5v ?? v cc ? 5.5v 2.5v ?? v cc ? 4.5v 1.8v ?? v cc ? 2.5v 11 t cld clock delay time 50 ? ns ? 12 t cle clock enable time 50 ? ns ? 13 t v output valid from clock low ? ? ? 50 100 160 ns ns ns 4.5v ?? v cc ? 5.5v 2.5v ?? v cc ? 4.5v 1.8v ?? v cc ? 2.5v 14 t ho output hold time 0 ? ns ( note 1 ) 15 t dis output disable time ? ? ? 40 80 160 ns ns ns 4.5v ?? v cc ? 5.5v ( note 1 ) 2.5v ?? v cc ? 4.5v ( note 1 ) 1.8v ?? v cc ? 2.5v ( note 1 ) 16 t hs hold setup time 20 40 80 ? ? ? ns ns ns 4.5v ?? v cc ? 5.5v 2.5v ?? v cc ? 4.5v 1.8v ?? v cc ? 2.5v note 1: this parameter is periodically sampled and not 100% tested. 2: this parameter is not tested but ensured by characterization. for endurance estimates in a specific application, please consult the total endurance? model which can be obtained from microchip?s web site at www.microchip.com. 3: t wc begins on the rising edge of cs after a valid write sequence and ends when the internal write cycle is complete.
25aa02e48/25AA02E64 ds20002123d-page 4 ? 2008-2013 microchip technology inc. table 1-3: ac test conditions 17 t hh hold hold time 20 40 80 ? ? ? ns ns ns 4.5v ?? v cc ? 5.5v 2.5v ?? v cc ? 4.5v 1.8v ?? v cc ? 2.5v 18 t hz hold low to output high-z 30 60 160 ? ? ? ns ns ns 4.5v ?? v cc ? 5.5v ( note 1 ) 2.5v ?? v cc ? 4.5v ( note 1 ) 1.8v ?? v cc ? 2.5v ( note 1 ) 19 t hv hold high to output valid 30 60 160 ? ? ? ns ns ns 4.5v ?? v cc ? 5.5v 2.5v ?? v cc ? 4.5v 1.8v ?? v cc ? 2.5v 20 t wc internal write cycle time (byte or page) ?5ms ( note 3 ) 21 ? endurance 1m ? e/w cycles 25c, v cc = 5.5v ( note 2 ) table 1-2: ac characteristics (continued) ac characteristics industrial (i): t a = -40c to +85c v cc = 1.8v to 5.5v param. no. sym. characteristic min. max. units test conditions note 1: this parameter is periodically sampled and not 100% tested. 2: this parameter is not tested but ensured by characterization. for endurance estimates in a specific application, please consult the total endurance? model which can be obtained from microchip?s web site at www.microchip.com. 3: t wc begins on the rising edge of cs after a valid write sequence and ends when the internal write cycle is complete. ac waveform: v lo = 0.2v ? v hi = v cc - 0.2v ( note 1 ) v hi = 4.0v ( note 2 ) c l = 100 pf ? timing measurement reference level input 0.5 v cc output 0.5 v cc note 1: for v cc ? 4.0v 2: for v cc ? 4.0v
? 2008-2013 microchip technology inc. ds20002123d-page 5 25aa02e48/25AA02E64 figure 1-1: hold timing figure 1-2: serial input timing figure 1-3: serial output timing cs sck so si hold 17 16 16 17 19 18 don?t care 5 high-impedance n + 2 n + 1 n n - 1 n n + 2 n + 1 n n n - 1 cs sck si so 6 5 8 7 11 3 lsb in msb in high-impedance 12 mode 1 , 1 mode 0 , 0 2 4 cs sck so 10 9 13 msb out isb out 3 15 don?t care si mode 1 , 1 mode 0 , 0 14
25aa02e48/25AA02E64 ds20002123d-page 6 ? 2008-2013 microchip technology inc. 2.0 functional description 2.1 principles of operation the 25aa02exx is a 256-byte serial eeprom designed to interface directly with the serial peripheral interface (spi) port of many of today?s popular microcontroller families, including microchip?s pic ? microcontrollers. it may also interface with microcon- trollers that do not have a built-in spi port by using discrete i/o lines programmed properly in software to match the spi protocol. the 25aa02exx contains an 8-bit instruction register. the device is accessed via the si pin, with data being clocked in on the rising edge of sck. the cs pin must be low and the hold pin must be high for the entire operation. table 2-1 contains a list of the possible instruction bytes and format for device operation. all instructions, addresses, and data are transferred msb first, lsb last. data (si) is sampled on the first rising edge of sck after cs goes low. if the clock line is shared with other peripheral devices on the spi bus, the user can assert the hold input and place the 25aa02exx in ?hold? mode. after releasing the hold pin, operation will resume from the point when the hold was asserted. 2.2 read sequence the device is selected by pulling cs low. the 8-bit read instruction is transmitted to the 25aa02exx followed by an 8-bit address. see figure 2-1 for more details. after the correct read instruction and address are sent, the data stored in the memory at the selected address is shifted out on the so pin. data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses to the slave. the internal address pointer automatically increments to the next higher address after each byte of data is shifted out. when the highest address is reached (ffh), the address counter rolls over to address 00h allowing the read cycle to be continued indefinitely. the read operation is terminated by raising the cs pin ( figure 2-1 ). 2.3 write sequence prior to any attempt to write data to the 25aa02exx, the write enable latch must be set by issuing the wren instruction ( figure 2-4 ). this is done by setting cs low and then clocking out the proper instruction into the 25aa02exx. after all eight bits of the instruction are transmitted, cs must be driven high to set the write enable latch. if the write operation is initiated immedi- ately after the wren instruction without cs driven high, data will not be written to the array since the write enable latch was not properly set. after setting the write enable latch, the user may proceed by driving cs low, issuing a write instruction, followed by the remainder of the address, and then the data to be written. up to 16 bytes of data can be sent to the device before a write cycle is necessary. the only restriction is that all of the bytes must reside in the same page. additionally, a page address begins with xxxx 0000 and ends with xxxx 1111 . if the internal address counter reaches xxxx 1111 and clock signals continue to be applied to the chip, the address counter will roll back to the first address of the page and over- write any data that previously existed in those locations. for the data to be actually written to the array, the cs must be brought high after the least significant bit (d0) of the n th data byte has been clocked in. if cs is driven high at any other time, the write operation will not be completed. refer to figure 2-2 and figure 2-3 for more detailed illustrations on the byte write sequence and the page write sequence respectively. while the write is in progress, the status register may be read to check the status of the wip, wel, bp1 and bp0 bits ( figure 2-6 ). attempting to read a memory array location will not be possible during a write cycle. polling the wip bit in the status register is recommended in order to determine if a write cycle is in progress. when the write cycle is completed, the write enable latch is reset. note: page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. physical page boundaries start at addresses that are integer multiples of the page buffer size (or ?page size?) and, end at addresses that are integer multiples of page size ? 1. if a page write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. it is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary.
? 2008-2013 microchip technology inc. ds20002123d-page 7 25aa02e48/25AA02E64 block diagram figure 2-1: read sequence si so sck cs hold wp status register i/o control memory control logic x dec hv generator eeprom array page latches y decoder sense amp. r/w control logic v cc v ss table 2-1: instruction set instruction name instruction format description read 0000 x011 read data from memory array beginning at selected address write 0000 x010 write data to memory array beginning at selected address wrdi 0000 x100 reset the write enable latch (disable write operations) wren 0000 x110 set the write enable latch (enable write operations) rdsr 0000 x101 read status register wrsr 0000 x001 write status register x = don?t care so si sck cs 0 234567891011 1 01 0 0 0 0 01 a 7 a 6 a 5 a 4 a 1 a 0 76543210 data out high-impedance a 3 a 2 address byte 12 13 14 15 16 17 18 19 20 21 22 23 instruction
25aa02e48/25AA02E64 ds20002123d-page 8 ? 2008-2013 microchip technology inc. figure 2-2: byte write sequence figure 2-3: page write sequence so si cs 0 234567891011 1 00 0 0 0 0 01 a 6 a 5 a 4 a 1 a 3 a 2 address byte 12 13 14 15 16 17 18 19 20 21 22 23 instruction data byte a 0 6 7 5 43 2 1 0 high-impedance twc sck a 7 si cs 91011 00 0 0 0 0 01 76543210 data byte 1 sck 0 234567 1 8 si cs 33 34 35 38 39 76543210 data byte n (16 max) sck 24 26 27 28 29 30 31 25 32 76543210 data byte 3 76543210 data byte 2 36 37 instruction address byte a 7 a 6 a 5 a 4 a 3 a 1 a 0 a 2 12 13 14 15 16 17 18 19 20 21 22 23
? 2008-2013 microchip technology inc. ds20002123d-page 9 25aa02e48/25AA02E64 2.4 write enable ( wren ) and write disable ( wrdi ) the 25aa02exx contains a write enable latch. see table 2-4 for the write-protect functionality matrix. this latch must be set before any write operation will be completed internally. the wren instruction will set the latch, and the wrdi will reset the latch. the following is a list of conditions under which the write enable latch will be reset: ? power-up ? wrdi instruction successfully executed ? wrsr instruction successfully executed ? write instruction successfully executed ?wp pin is brought low figure 2-4: write enable sequence ( wren ) figure 2-5: write disable sequence ( wrdi ) sck 0 234567 1 si high-impedance so cs 01 0000 0 1 sck 0 234567 1 si high-impedance so cs 01 0000 0 0
25aa02e48/25AA02E64 ds20002123d-page 10 ? 2008-2013 microchip technology inc. 2.5 read status register instruction (rdsr) the read status register instruction ( rdsr ) provides access to the status register. see figure 2-6 for the rdsr timing sequence. the status register may be read at any time, even during a write cycle. the status register is formatted as follows: table 2-2: status register the write-in-process (wip) bit indicates whether the 25aa02exx is busy with a write operation. when set to a ? 1 ?, a write is in progress, when set to a ? 0 ?, no write is in progress. this bit is read-only. the write enable latch (wel) bit indicates the status of the write enable latch and is read-only. when set to a ? 1 ?, the latch allows writes to the array, when set to a ? 0 ?, the latch prohibits writes to the array. the state of this bit can always be updated via the wren or wrdi commands regardless of the state of write protection on the status register. these commands are shown in figure 2-4 and figure 2-5 . the block protection (bp0 and bp1) bits indicate which blocks are currently write-protected. these bits are set by the user issuing the wrsr instruction, which is shown in figure 2-7. these bits are nonvolatile and are described in more detail in table 2-3 . figure 2-6: read status register timing sequence ( rdsr ) 7 654 3 2 1 0 ? ???w/rw/r r r x xxx bp1 bp0 wel wip w/r = writable/readable. r = read-only. so si cs 91011 12131415 11 0 0 0 0 00 7654 2 10 instruction data from status register high-impedance sck 0 234567 18 3
? 2008-2013 microchip technology inc. ds20002123d-page 11 25aa02e48/25AA02E64 2.6 write status register instruction ( wrsr ) the write status register instruction ( wrsr ) allows the user to write to the nonvolatile bits in the status register as shown in ta b l e 2 - 2 . see figure 2-7 for the wrsr timing sequence. four levels of protection for the array are selectable by writing to the appropriate bits in the status register. the user has the ability to write-protect none, one, two, or all four of the segments of the array as shown in table 2-3 . table 2-3: array protection figure 2-7: write status register timing sequence ( wrsr ) bp1 bp0 array addresses write-protected 00 none 01 upper 1/4 (c0h-ffh) 10 upper 1/2 (80h-ffh) 11 all (00h-ffh) so si cs 91011 12131415 01 0 0 0 0 00 7654 210 instruction data to status register high-impedance sck 0 234567 1 8 3
25aa02e48/25AA02E64 ds20002123d-page 12 ? 2008-2013 microchip technology inc. 2.7 data protection the following protection has been implemented to prevent inadvertent writes to the array: ? the write enable latch is reset on power-up ? a write enable instruction must be issued to set the write enable latch ? after a byte write, page write or status register write, the write enable latch is reset ?cs must be set high after the proper number of clock cycles to start an internal write cycle ? access to the array during an internal write cycle is ignored and programming is continued 2.8 power-on state the 25aa02exx powers on in the following state: ? the device is in low-power standby mode (cs = 1 ) ? the write enable latch is reset ? so is in high-impedance state ? a high-to-low-level transition on cs is required to enter active state table 2-4: write-protec t functionality matrix wp (pin 3) wel (sr bit 1) protected blocks unprotected blocks status register 0 (low) x protected protected protected 1 (high) 0 protected protected protected 1 (high) 1 protected writable writable x = don?t care
? 2008-2013 microchip technology inc. ds20002123d-page 13 25aa02e48/25AA02E64 3.0 pre-programmed eui-48? or eui-64? node address the 25aa02exx is programmed at the factory with a globally unique node address stored in the upper 1/4 of the array and write-protected through the status register. the remaining 1,536 bits are available for application use. figure 3-1: memory organization 3.1 factory-programmed write protection in order to help guard against accidental corruption of the node address, the bp1 and bp0 bits of the status register are programmed at the factory to ? 0 ? and ? 1 ?, respectively, as shown in the following table: this protects the upper 1/4 of the array (0xc0 to 0xff) from write operations. this array block can be utilized for writing by clearing the bp bits with a write status register ( wrsr ) instruction. note that if this is per- formed, care must be taken to prevent overwriting the node address value. 3.2 eui-48 ? node address (25aa02e48) the 6-byte eui-48? node address value of the 25aa02e48 is stored in array locations 0xfa through 0xff, as shown in figure 3-2 . the first 3 bytes are the organizationally unique identifier (oui) assigned to microchip by the ieee registration authority. currently, microchip?s ouis are 0x0004a3 and 0x001ec0, though this will change as addresses are exhausted. the remaining three bytes are the extension identifier, and are generated by microchip to ensure a globally unique, 48-bit value. 3.2.1 eui-64? support using the 25aa02e48 the pre-programmed eui-48 node address of the 25aa02e48 can easily be encapsulated at the applica- tion level to form a globally unique, 64-bit node address for systems utilizing the eui-64 standard. this is done by adding 0xfffe between the oui and the extension identifier, as shown below. figure 3-2: eui-48 node address physic al memory map example (25aa02e48) 7654 3 2 1 0 xxxx bp1 bp0 wel wip ???? 01 ?? 00h c0h ffh write-protected node address block standard eeprom note: as an alternative, the 25AA02E64 fea- tures an eui-64 node address that can be used in eui-64 applications directly with- out the need for encapsulation, thereby simplifying system software. see section 3.3 ?eui-64? node address (25AA02E64)? for details. fah ffh 24-bit organizationally unique identifier 24-bit extension identifier 00h 04h a3h 12h 34h 56h corresponding eui-48? node address: 00-04-a3-12-34-56 description data array address corresponding eui-64? node address after encapsulation: 00-04-a3-ff-fe-12-34-56
25aa02e48/25AA02E64 ds20002123d-page 14 ? 2008-2013 microchip technology inc. 3.3 eui-64 ? node address (25AA02E64) the 8-byte eui-64? node address value of the 25AA02E64 is stored in array locations 0xf8 through 0xff, as shown in figure 3-3 . the first three bytes are the organizationally unique identifier (oui) assigned to microchip by the ieee registration authority. cur- rently, microchip?s ouis are 0x0004a3 and 0x001ec0, though this will change as addresses are exhausted. the remaining five bytes are the extension identifier, and are generated by microchip to ensure a globally unique, 64-bit value. figure 3-3: eui-64 node address physic al memory map example (25AA02E64) note: in conformance with ieee guidelines, microchip will not use the values 0xfffe and 0xffff for the first two bytes of the eui-64 extension identifier. these two values are specifically reserved to allow applications to encapsulate eui-48 addresses into eui-64 addresses. f8h ffh 24-bit organizationally unique identifier 40-bit extension identifier 00h 04h a3h 12h 34h 56h corresponding eui-64? node address: 00-04-a3-12-34-56-78-90 description data array address 78h 90h
? 2008-2013 microchip technology inc. ds20002123d-page 15 25aa02e48/25AA02E64 4.0 pin descriptions the descriptions of the pins are listed in tab l e 4 - 1 . table 4-1: pin function table 4.1 chip select (cs ) a low level on this pin selects the device. a high level deselects the device and forces it into standby mode. however, a programming cycle which is already initiated or in progress will be completed, regardless of the cs input signal. if cs is brought high during a program cycle, the device will go into standby mode as soon as the programming cycle is complete. when the device is deselected, so goes to the high-impedance state, allowing multiple parts to share the same spi bus. a low-to-high transition on cs after a valid write sequence initiates an internal write cycle. after power- up, a low level on cs is required prior to any sequence being initiated. 4.2 serial output (so) the so pin is used to transfer data out of the 25aa02exx. during a read cycle, data is shifted out on this pin after the falling edge of the serial clock. 4.3 write-protect (wp ) the wp pin is a hardware write-protect input pin. when it is low, all writes to the array or status reg- ister are disabled, but any other operations function normally. when wp is high, all functions, including nonvolatile writes operate normally. at any time, when wp is low, the write enable reset latch will be reset and programming will be inhibited. however, if a write cycle is already in progress, wp going low will not change or disable the write cycle. see table 2-4 for the write-protect functionality matrix. 4.4 serial input (si) the si pin is used to transfer data into the device. it receives instructions, addresses and data. data is latched on the rising edge of the serial clock. 4.5 serial clock (sck) the sck is used to synchronize the communication between a master and the 25aa02exx. instructions, addresses or data present on the si pin are latched on the rising edge of the clock input, while data on the so pin is updated after the falling edge of the clock input. 4.6 hold (hold ) the hold pin is used to suspend transmission to the 25aa02exx while in the middle of a serial sequence without having to retransmit the entire sequence again. it must be held high any time this function is not being used. once the device is selected and a serial sequence is underway, the hold pin may be pulled low to pause further serial communication without resetting the serial sequence. the hold pin must be brought low while sck is low, otherwise the hold function will not be invoked until the next sck high-to- low transition. the 25aa02exx must remain selected during this sequence. the si, sck and so pins are in a high-impedance state during the time the device is paused and transitions on these pins will be ignored. to resume serial communication, hold must be brought high while the sck pin is low, otherwise serial communication will not resume. lowering the hold line at any time will tri-state the so line. name soic sot-23 function cs 1 5 chip select input so 2 4 serial data output wp 3 ? write-protect pin v ss 4 2 ground si 5 3 serial data input sck 6 1 serial clock input hold 7 ? hold input v cc 8 6 supply voltage
25aa02e48/25AA02E64 ds20002123d-page 16 ? 2008-2013 microchip technology inc. 5.0 packaging information 5.1 package marking information part number 1st line marking code soic sot-23 i temp. i temp. 25aa02e48 25a2e48t 20nn 25AA02E64 25a2e64t aaaay 8-lead soic xxxxyyww xxxxxxxt nnn example: sn 1327 25a2e48i 1l7 3 e 6-lead sot-23 (25aa02e48) xxnn example: 20l7 6-lead sot-23 (25AA02E64) xxxxy example: aaaa3 wwnnn 271l7 legend: xx...x part number or part number code t temperature (i, e) y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code (2 characters for small packages) pb-free jedec designator for matte tin (sn) note : for very small packages with no room for the pb-free jedec designator , the marking will only appear on the outer carton or reel label. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e note: please visit www.microchip.com/pbfree for the latest information on pb-free conversion. * standard otp marking consists of microchip part number, year code, week code, and traceability code.
? 2008-2013 microchip technology inc. ds20002123d-page 17 25aa02e48/25AA02E64 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
25aa02e48/25AA02E64 ds20002123d-page 18 ? 2008-2013 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2008-2013 microchip technology inc. ds20002123d-page 19 25aa02e48/25AA02E64
25aa02e48/25AA02E64 ds20002123d-page 20 ? 2008-2013 microchip technology inc. b e 4 n e1 pin1idby laser mark d 1 2 3 e e1 a a1 a2 c l l1
? 2008-2013 microchip technology inc. ds20002123d-page 21 25aa02e48/25AA02E64 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
25aa02e48/25AA02E64 ds20002123d-page 22 ? 2008-2013 microchip technology inc. appendix a: revision history revision a (12/08) original release of this document. revision b (04/10) removed preliminary status; revised section 2.0; add sentence to section 3.0; add sot-23 land pattern. revision c (12/2012) revised table 1-2, param. 21. revision d (4/2013) added 25AA02E64 part number.
? 2008-2013 microchip technology inc. ds20002123d-page 23 25aa02e48/25AA02E64 the microchip web site microchip provides online support via our www site at www.microchip.com. this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com, click on customer change notification and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support ? development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://support.microchip.com
25aa02e48/25AA02E64 ds20002123d-page 24 ? 2008-2013 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds20002123d 25aa02e48/25AA02E64 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document?
? 2008-2013 microchip technology inc. ds20002123d-page 25 25aa02e48/25AA02E64 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . part no. x /xx package tape & reel device device: 25aa02e48 = 25AA02E64 = 2k-bit, 1.8v, 16-byte page, spi serial eeprom with eui-48? node identity 2k-bit, 1.8v, 16-byte page, spi serial eeprom with eui-64? node identity tape & reel: blank = t= standard packaging tape & reel temperature range: i= -40 ? c to+85 ? c package: sn = ot = plastic soic (3.90 mm body), 8-lead sot-23, 6-lead (tape and reel only) examples: a) 25aa02e48-i/sn = 2k-bit, 16-byte page, 1.8v serial eeprom with eui-48 node identity, industrial temp., soic package b) 25aa02e48t-i/sn = 2k-bit, 16-byte page, 1.8v serial eeprom with eui-48 node identity, industrial temp., tape & reel, soic package c) 25aa02e48t-i/ot = 2k-bit, 16-byte page, 1.8v serial eeprom with eui-48 node identity, industrial temp., tape & reel, sot-23 package d) 25AA02E64-i/sn = 2k-bit, 16-byte page, 1.8v serial eeprom with eui-64 node identity, industrial temp., soic package e) 25AA02E64t-i/sn = 2k-bit, 16-byte page, 1.8v serial eeprom with eui-64 node identity, industrial temp., tape & reel, soic package f) 25AA02E64t-i/ot = 2k-bit, 16-byte page, 1.8v serial eeprom with eui-64 node identity, industrial temp., tape & reel, sot-23 package ? x temperature
25aa02e48/25AA02E64 ds20002123d-page 26 ? 2008-2013 microchip technology inc. notes:
? 2008-2013 microchip technology inc. ds20002123d-page 27 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mtp, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. analog-for-the-digital age, app lication maestro, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, sqi, serial quad i/o, total endurance, tsharc, uniwindriver, wiperlock, zena and z-scale are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. gestic and ulpp are registered trademarks of microchip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2008-2013, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 9781620771525 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 ==
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